1. Field of the Invention
The present invention relates to a method for fabricating a ferroelectric memory.
2. Background of the Related Art
Currently, there have been wide researches for application of a P(L)ZT or SBT thin film to a memory, such as an FRAM (Ferroelectric Random Access Memory). As a high temperature and an oxygen environment are involved in forming the PZT thin film, metals such as Pt, or oxides such as RuO.sub.2 or IrO.sub.2, which are stable in an oxygen environment, are widely used as an electrode material. In the fabrication of the FRAM, technologies for forming and etching the electrode and the ferroelectric film are essential. Though there has been researches for dry etching of the PZT thin film or the Pt thin film partly, there have been difficulties in formation of the capacitor for use in the FRAM because present technologies have a low etch rate, a poor etch selectivity to photoresist, and a fence formed at sidewall after an etching. Though there have been researches for fabricating the capacitor using SiO.sub.2 as a mask material for assuring an etch selectivity partly, the assurance of an adequate etch selectivity for fabricating the capacitor for FRAM has been failed(etch selectivity of the Pt film to the SiO.sub.2 is .apprxeq.1). Therefore, researches for an appropriate etch mask which can suppress formation of a fence after etching and has an excellent etch selectivity are required.
FIG. 1 illustrates a typical PRAM, which can be fabricated by a process for fabricating a transistor using a CMOS process and a process for fabricating a ferroelectric capacitor. However, as shown in FIG. 2, unless CMP(Chemical Mechanical Polishing) is used in fabrication of the transistor using the CMOS process, a great step is formed by a field oxide and a polysilicon. In general, coating of the PZT thin film by sol-gel method is done in spin coating. The spin coating causes a thin film thicker in a grooved portion and thinner in a ridged portion, which causes the following problems when the thin film is etched.
Even after completion of etching the thinner portion of the PZT thin film, a thick PZT film still remains at the thicker portion of the PZT thin film. And, if the film remained at the thicker portion of the PZT thin film is etched, BPSG(Boron Phosphorus Silicate Glass) and an underlying electrode at the thinner portion of the PZT thin film will be also etched seriously. In general, as the BPSG is etched faster than the PZT thin film in a Cl.sub.2 /CF.sub.4 gas environment which is used in etching the PZT thin film, a problem of an excessive etching of the BPSG becomes more serious. Moreover, since a high density device packing leads an etch rate of a groove portion slower than a ridge portion, the problem becomes more serious. For solving the problem, a CMP can be applied before fabrication of the capacitor of the PZT for planarizing the steps after deposition of the BPSG but the CMP costs high and has not established process conditions which are enough for application to a mass production, yet.